Synopsys Inc. announced the expansion of its memory Verification IP (VIP) portfolio to include key titles for the mobile industry. Synopsys memory VIP is based on a native SystemVerilog architecture to enable enhanced ease of use, integration and configurability. With these advanced features, project teams using the JEDEC UFS, MIPI® UniProSM and JEDEC eMMC protocols can further accelerate verification closure of mobile block, subsystem and system-on-chip (SoC) designs.

VIP for the emerging UFS and UniPro protocols also includes self-contained compliance test suites to accelerate verification closure and eliminate the tasks of developing a verification environment and tests. The test suites are delivered as native SystemVerilog source code for improved reuse, extensibility and debug. The JEDEC eMMC VIP includes support for eMMC Card and Host.

All verification IP and test suites are based on a consistent SystemVerilog UVM architecture to enable easy adoption. The company's broad portfolio of bus, interface and memory VIP includes built-in coverage and verification plans to enable coverage closure. It also includes support for Verdi® Protocol Analyzer to provide protocol-aware debug.

Synopsys VIP for the JEDEC UFS, MIPI UniPro and JEDEC eMMC memory protocol specifications provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence. Availability: Synopsys Verification IP for UFS, MIPI UniPro and eMMC are available standalone and as part of the Synopsys VIP Library as well as in the Verification Compiler™ product. The Synopsys DesignWare® digital controllers for UFS, MIPI UniPro and eMMC are also available now.