Synopsys Inc. announced the availability of its multiprotocol DesignWare(R) Enterprise 10G PHY IP to address the connectivity needs of a broad range of high-end, energy efficient networking and computing applications. Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nanometer (nm) Enterprise 10G PHY supports multiple interface standards, including PCI Express(R) (PCIe(R)) 3.0 and 10GBASE-KR, for a flexible interconnect solution. The new DesignWare IP also implements a multi-lane PHY architecture to support data rates from 1.25 Gbps to 10.3 Gbps per lane, with capabilities to aggregate to 40 Gbps and 100 Gbps Ethernet, giving designers a proven, scalable solution to address the growing demand for additional networking bandwidth in high-speed systems-on-chips (SoCs).

The DesignWare Enterprise 10G PHY offers a modular design with a highly configurable physical coding sub-layer (PCS) capable of bifurcation and aggregation. Its analog front-end includes multi-tap decision feedback equalization (DFE) and continuous time linear equalization (CTLE), which enhance signal integrity in high throughput communication channels. The DesignWare Enterprise 10G PHY is optimized for area, power and width to ease integration into the rest of the SoC.

The Enterprise 10G PHY is part of Synopsys' complete PCI Express 3.0 and 10G Ethernet solutions, each of which include a PCS, controller and verification IP. The PHY's support for 10GBASE-KR includes physical medium attachment (PMA), auto negotiation (AN), PCS, forward error correction (FEC) and energy-efficient Ethernet (EEE). Providing comprehensive 10GBASE-KR support, including the optional EEE and FEC features, enables SoC designers to single-source IP solutions to help ensure interoperability while reducing risk and time-to-market.