STATS ChipPAC Ltd. and United Microelectronics Corporation announced the world's first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration. The 3D chip stack, consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip, successfully reached a major milestone on package-level reliability assessment. This success demonstrates a total solution for reliable 3D IC manufacturing through the combination of UMC's foundry and STATS ChipPAC's packaging services.

UMC and STATS ChipPAC's proven open ecosystem 3D IC approach sets an important standard for collaboration within the industry supply chain to achieve mutual success. Under the 3D IC open development project with STATS ChipPAC, UMC provides the FEOL wafer manufacturing, with a foundry grade fine pitch, high density TSV process that can be seamlessly integrated with UMC's 28nm poly SiON process flow. The know-how developed will be applied towards implementation on the foundry's 28nm High-K/metal gate process.

For MEOL and BEOL, STATS ChipPAC performs the wafer thinning, wafer backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking.