CEVA, Inc. announced that CEVA-BX, its new all-purpose, hybrid DSP /Controller architecture to address new algorithms of digital signal processing in voice, video, communication, sensing and digital signal control applications. Offering general purpose DSP capabilities required for motor control and electrification, the CEVA-BX architecture extends CEVA's market reach into the burgeoning automotive and industrial markets currently underserved by legacy DSPs or MPU/MCUs with low performance DSP co-processing. CEVA-BX offers a new breed of DSP architecture, combining the inherent low power requirements of DSP kernels with the high-level programming and compact code size requirements of a large control code base. Using an 11-stage pipeline and 5-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz at TSMC 7nm process node using common standard cells and memory compilers. The CEVA-BX Instruction Set Architecture (ISA) incorporates support for Single Instruction Multiple Data (SIMD) widely used in neural network inference, noise reduction and echo cancellation, as well as half, single and double precision floating point units for high accuracy sensor fusion and positioning algorithms.