Cadence Design Systems Inc. announced that Kandou Bus has fully tested and characterized a 28nm high-speed SerDes PHY IP design named, "Glasswing," that was implemented using the Cadence® mixed-signal signoff flow. Silicon results confirm that the design can deliver up to 25Gbps per data bus bit, enabling a throughput of 125Gbps over the interface. These specs were achieved while Kandou also reduced dynamic power by 3-5X.

To meet strict timing and power specifications for this advanced analog/mixed-signal design, Kandou used the OpenAccess-based Cadence Virtuoso® Digital Signoff Timing Solution, which is integrated with the Tempus™ Timing Signoff Solution to provide timing signoff accuracy. In addition, Kandou used the Virtuoso Digital Signoff Power Solution, which is integrated with the Voltus™ IC Power Integrity Solution and the Voltus-Fi Custom Power Integrity Solution to provide power signoff accuracy. The Quantus™ QRC Extraction Solution and the Spectre® Accelerated Parallel Simulator (APS) provided Kandou with a foundry-certified, silicon-accurate, analog/mixed-signal signoff solution.

Using Cadence's advanced mixed-signal signoff solution, Kandou achieved timing and power results that correlated within 1% of silicon. The Cadence tools also eliminated the need for further silicon debugging and allowed Kandou to produce a reliable design that yielded a transmission bit error rate (BER) under 1E-15. Kandou was able to achieve their aggressive data throughput goals while reducing power consumption when compared with a traditional, standard DDR3 interface.